It is desirable to increase the packing density of ICs, e.g., large-scale integrated (LSI) circuits, in circuit boards because this facilitates the miniaturization of electrical devices. Unfortunately, many IC attachment processes require a redistribution wiring layer (RDL) that redirects interconnects contacting the active components of the IC to bond pads on peripheral locations of IC. Significant resources and board space are devoted to produce and accommodate the RDL. There is a limit, however, to the number of bond pads that can be situated around the periphery of the IC. In some cases, therefore, the IC die is maintained at a certain minimum size simply so that there is enough space for the surrounding bond pads.
Accordingly, what is needed in the art is method to increase the packing density of ICs on a circuit board without the complexities and costs inherent in today's attachment technologies.